Patent decision

BL number

O/093/07

Concerning rights in

GB0317109.7

Hearing Officer

Mr P Slater

Decision date

30 March 2007

Person(s) or Company(s) involved

Hewlett Packard Development Company L P

Provisions discussed

PA 1977 Section 1(2)(c)

Keywords

Excluded fields (refused)

Related Decisions

None

Summary

The invention relates to the computer simulation of integrated circuits and in particular the creation of circuit models on which to run timing software. It is well known that for accurate simulation and testing, timing software requires circuit models which incorporate the effects of parasitic resistance and capacitance. However, it is often desirable to simplify the model by eliminating elements of resistance and capacitance, so that the timing software will run in reasonable time and memory. The invention provides a new way of simplifying circuit models in which the various inputs to the so called “active elements” e.g. transistors are examined to see if they can be simplified by removing elements of resistance. The time constant at each input is calculated and compared to a threshold value. If the time constant is below the threshold, then the resistance present at the input is removed from the circuit and the remaining capacitances where possible are combined. The process is then repeated in an iterative manner until no further simplification of the model is possible.

The hearing officer held that the invention failed the third step of the Aerotel/Macrossan [2006] EWCA Civ 1371 test because the contribution, “a new method of simplifying a circuit”, related to no more than a method for performing a mental act and/or a computer program as such.

Full decision O/093/07 38Kb